The central processing unit (CPU) and memory inter-chip interface is very important for system performance and power. As systems require more performance, the data traffic between a CPU and local memory increases, pushing up the inter-chip interface speed for high data bandwidth. However, a high-speed inter-chip interface often suffers from clock jitter and clock-to-signal skews.
FIG. 1 is a simplified cross-sectional view of a stacked POP (Package-On-Package) system comprising two memory chips (dice) labeled 102 and 104, and a logic chip (die) labeled 106. The logic chip 106 comprises a CPU (not shown), where memory chips 102 and 104 are part of the memory hierarchy available to the CPU.
The memory chips 102 and 104 are electrically connected to the logic chip 106. Wires 107 electrically connect the memory chips to contact pads (not shown) on the package substrate 108, and vias (not shown) in the package substrate 108 provide electrical connection to the package balls 110. Package balls 110 provide electrical connection to the logic chip 106 by way of interconnects (not shown) on the package substrate 112 and by way of the package balls 114.
Package balls 116 are electrically connected to the package balls 114 by way of vias (not shown) in the package substrate 112 so that the logic chip 106 may be electrically connected to other packaged integrated circuits by way of a printed circuit board (not shown).
Many mobile systems have multiple memory channels, where it is common for each memory channel interface to have a 32-bit I/O (Input/Output) width. The physical implementation of this interface is segmented across the dice in a stacked package. This distributed segmentation feature is illustrated in FIG. 2, which abstracts the memory-to-CPU interface in the POP system of FIG. 1.
Referring to FIG. 2, the plane labeled 202 represents a memory chip, and the plane labeled 204 represents a logic chip. An inter-chip interface on the memory chip 202 is segmented into two structures labeled 206 and 208. This inter-chip interface includes interconnects for a clock signal, command signals, power rails, ground rails, address signals, write data signals, and read data signals, for example.
The corresponding inter-chip interface on the logic chip 204 is segmented in the same way as on the memory chip, and is abstracted by the two structures labeled 210 and 212. The line labeled 214 abstracts the interconnects between the structures 206 and 210, and the line labeled 216 abstracts the interconnects between the structures 208 and 212. Accordingly, the lines 214 and 216 will be referred to as interconnects. The structures in the cross-sectional view of FIG. 1 corresponding to the combination of the interconnects 214 and 216 are the wires 107, the vias within the package substrate 108, the package balls 110, the interconnects on the package substrate 112, and the package balls 114.
A reason for physically segmenting the inter-chip interface is because of constraints imposed by the layout of die pads and package balls. The functional unit 218 abstracts the clock source and set of drivers to drive the inter-chip interface. For proper operation, the clock source represented by the functional unit 218 must maintain the same clock phase over the two portions of the inter-chip interface, even though these two portions of the inter-chip interface are physically placed near opposite ends of the logic chip 204.
The structures represented by the labels 206, 208, 210, 212, 214, and 216 contribute to the overall electrical length of the inter-chip interface for coupling the memory chip 202 to the logic chip 204. The physical distribution and segmentation of this single interface over the two chips as indicated in FIG. 2 contribute to clock signal jitter skews, which limits the overall system frequency and performance.